This application claims the priority of Korean Patent Application No. 2002-73815 filed on Nov. 26, 2002 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a nonvolatile memory device, and more particularly, to a method for operating a NOR-type flash memory device having silicon-oxide-nitride-oxide-semiconductor (SONOS) cells.
2. Description of the Related Art
Nonvolatile semiconductor memory devices can have a variety of types which have a common characteristic in that after an applied power is removed from the nonvolatile semiconductor memory devices, the nonvolatile semiconductor memory devices can retain stored information. Of such nonvolatile semiconductor memory devices, a flash memory device can be largely classified into a NAND-type flash memory device and a NOR-type flash memory device according to the array form of unit cells. The NOR-type flash memory device has attracted much attention in terms of the advantageousness to the high integration. Unit cells of a flash memory device have been generally floating gate cells.
FIG. 1 is a schematic cross-sectional view explaining a conventional floating gate cell. As shown in FIG. 1, in the conventional floating gate cell, a source 21 and a drain 25 are formed in a substrate 10. A floating gate 33 and a control gate 37 are formed over a portion of the substrate 1 between the source 21 and the drain 25. A gate dielectric layer 31 is formed of silicon oxide between the floating gate 33 and the substrate 10. An interlayer insulating layer 35 is formed of oxide-nitride-oxide (ONO) between the floating gate 33 and the control gate 37. A bit line 55 is electrically connected to the drain 25 via a contact 51 the rest of the structure being surrounded by an insulating layer 40.
The floating gate cell stores information by charging/discharging the floating gate 33 to dualize a threshold voltage Vth. In other words, when the floating gate 33 is charged with electrons, a voltage is applied to the control gate 37. Then, the applied voltage is screened by the charged electrons, and thus a threshold voltage Vth of a channel under the floating gate 33 and the control gate 37 increases. In contrast, in the case where the floating gate 33 has no electrons, the threshold voltage Vth is decreases. Due to an increase or a decrease in the threshold voltage Vth, a digital signal of 1/0 is stored.
However, since the control gate 37 is stacked over the floating gate 33, the floating gate cell has several limitations. For example, a complicated process is required to form the floating gate 33 over the control gate 37. Also, it is difficult to highly integrate a memory device. Thus, much research on realizing a new type of flash memory device has been attempted.